One interesting topic of discussion is whether to use synchronous or asynchronous reset in design. In synchronous reset design, we use reset signal in the D path of flop. Hence, the assertion of reset ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Metastability can cause a spacecraft electronic failure. It may render a very expensive spacecraft/satellite unusable and if the spacecraft is manned, there could be lives in danger. A simple D ...

Clock domain crossings are significant sources of field system failures. Despite this fact, designs continue to be released without fully verified CDCs. A false sense of security resulting from ...