Nature

Low-cost and nanoscale non-volatile memory concept for future silicon chips

The ideal semiconductor memory for future silicon integrated circuits unifies the qualities of the different memory technologies of today: it should have the high speed of static random access memory ...
Electronics Weekly

LETI integrates III-V lasers on 200mm wafers using CMOS flow

Leti has integrated hybrid III-V silicon lasers on 200mm wafers using standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V ...
sciencex

Towards a process flow for monolithic CFET transistor architectures

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...
Electronics Weekly

CMOS will cut cost of integrated photonics, says Leti

French research group Leti has demonstrated a III-V semiconductor fabrication technique which it says will simplify the production of lasers. Leti says it has integrated hybrid III-V silicon lasers on ...
EDN

Performance grows with integration

The manufacturing process flow has been designed to allow all standard CMOS steps to occur at the front end of the process, with the micromachining steps performed after the circuitry is completed.
EDN

Mixed-signal design flow enables RF CMOS chip

Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a ...
Design-Reuse

X-FAB Partners With Akustica to Deliver World's First CMOS MEMS Single-Chip Microphones

X-FAB to Provide Foundry Services for Akustica's Family of CMOS MEMS Silicon Microphone Chips ERFURT, GERMANY and PITTSBURGH, PA -- May 31, 2006 -- Akustica, Inc., a pioneer in acoustic system-on-chip ...
Nanowerk

IMEC reports progress on simplified high-k/metal gate process for the 32nm node

(Nanowerk News) At today's VLSI Symposium, IMEC reports an improved performance for its planar CMOS using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32nm CMOS node. The ...
Electronic Design

IEDM sees transistor, memory, laser innovations

The International Electron Devices Meeting (IEDM) held Dec. 2-6, 2017, in San Francisco offered imec and Leti an opportunity to disclose several innovations. imec announced three new developments: ...
Electronic Design

Simplified High-k/Metal-Gate Process Increases Planar CMOS Speed

IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and ...
Design-Reuse

Radiation Hardened SRAM Designed by RedCat Devices and Fabricated in TowerJazz's 0.18um ...

Developed technology in TowerJazz commercial foundry opens multi-billion markets requiring specific components able to withstand high dose radiation Applications include electronics for communication, ...