Implementing a Partial Reconfiguration Design within Qsys for Intel® FPGAs

Design a Qsys System Using the Nios® II processor SD Card Interface

High-level design methods can dramatically increase your productivity. Now that technologies like high-level synthesis (HLS) have gone mainstream, we can make some serious improvements to our FPGA design process. In this episode of Chalk Talk, Amelia Dalton chats with Tim Vanevenhoven of Xilinx about how the new HLx editions of Vivado Design suite are taking high-level design mainstream. (sponsored by Xilinx) For more information: http://bit.ly/1pqh2ZB | EE Journal